The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body with field insulation regions formed by grooves filled with insulating material, by which method the grooves are etched into the semiconductor body with the use of an etching mask formed on an auxiliary layer provided on a surface of the semiconductor body, the auxiliary layer is removed from the portion of the surface situated next to the etching mask and from an edge of the surface situated below the etching mask, and a layer of the insulating material is deposited on the semiconductor body, whereby the grooves are filled and the edge of the surface situated below the etching mask is covered, after which the semiconductor body is subjected to a treatment by which material is removed parallel to the surface down to said auxiliary layer and finally the remaining portion of the auxiliary layer is removed.
Since the material reduction which takes place parallel with the surface of the semiconductor body is stopped the moment the auxiliary layer is reached, the insulated material deposited on the edge of the surface situated below the etching mask is not removed. Field insulation regions are thus formed which extend over an edge of active regions of the semiconductor body surrounded by the field insulation regions. These field insulation regions may be provided by processes in which no treatments at temperatures higher than 650 .degree. C. are required. Doping profiles already present in the semiconductor body, accordingly, are not interfered with by this method of providing the field oxide regions.
Doped surface zones may subsequently be formed in the active regions of the semiconductor body surrounded by the field insulation regions. For example, a layer of a doped semiconductor material is deposited on the semiconductor body then, after which the semiconductor body is subjected to a heat treatment whereby dopant diffuses from this layer into the semiconductor body. Since the edge of the active regions is covered by a strip of insulating material during this, it is prevented that dopants penetrate to an undesirable depth into the edge of the active regions during this heat treatment. This renders it impossible for pn junctions already present in the active regions to be short-circuited.
JP-A-63/185043 discloses a method of the kind mentioned in the opening paragraph whereby the semiconductor body is subjected to an isotropic etching treatment before the grooves are etched into the semiconductor body, which treatment is continued until the auxiliary layer has been removed both from the portion of the surface situated next to the etching mask and from the edge of the surface situated below the mask. The grooves are then etched into the semiconductor body in that the latter is subjected to an anisotropic etching treatment.
A pattern of electric conductors may be applied on the active regions which were thus formed and surrounded by the field insulation regions. The semiconductor body is then covered with a layer of electrically conducting material which is subsequently provided with a photoresist mask corresponding to the pattern to be formed, after which the pattern is etched into the electrically conducting layer. The electric conductors formed interconnect inter alia doped surface zones. It is found in practice that short-circuits may occur in the pattern of electric conductors thus provided.